1. Field of the Invention
The present invention relates generally to the field of nonvolatile memory devices for use in computers and other devices. More particularly, the present invention relates to nonvolatile memory arrays that use magnetic memory elements as individual memory cells.
2. Description of the Related Art
Certain types of magnetic memory cells that use the magnetic state of a ferromagnetic region for altering the electrical resistance of materials located near the ferromagnetic region are collectively known as magnetoresistive (MR) memory cells. An array of magnetic memory cells is often called a magnetic random access memory (MRAM).
In comparison to metallic MR memory cells, which are based on giant magnetoresistance (GMR) or anisotropic magnetoresistance (AMR) devices, MRAM memory cells are based on magnetic tunnel junction (MTJ) devices and rely on substantially different physical principles. For example, GMR devices include at least two ferromagnetic layers that are separated by a thin metallic layer. In contrast, an MTJ device has two ferromagnetic layers that are separated by a thin insulating tunnel barrier. The magnetoresistance of an MTJ device results from a spin-polarized tunneling of conduction electrons between the two ferromagnetic layers that depends on the relative orientation of the magnetic moments of the two ferromagnetic layers. Another important distinction between GMR and MTJ devices is that current flows parallel to the thin film layers forming a GMR device, whereas current flows perpendicularly to the thin film layers forming an MTJ device.
FIG. 1A shows a portion of a conventional MRAM array that uses conventional magnetoresistive memory cells, such as disclosed by U.S. Pat. No. 5,640,343 to Gallagher et al. (the Gallagher '343 patent). The MRAM array shown in FIG. 1A includes a set of electrically conductive traces 1-3 in a horizontal plane that function as parallel word lines and a set of electrically conductive traces 4-8 in another horizontal plane that function as parallel bit lines. The word lines are oriented in a different direction from the bit lines, preferably at a right angle, so that the two sets of lines intersect when viewed from above. The MRAM array of FIG. 1A is referred to as a cross point array because memory cells are placed at the intersection point of crossing lines. The MRAM array of FIG. 1A is formed on a substrate (not shown), such as a silicon, on which there would be other circuitry (also not shown). For clarity, a layer of insulative material that is located between the bit lines and word lines within the MRAM other than the intersecting regions is not shown. While three word lines and six bit lines are illustrated in FIG. 1A, the total number of lines is typically much larger.
A conventional memory cell 10 is located at each crossing point of the word lines and bit lines within an intersection region that is vertically spaced between the respective sets of lines. FIG. 1B shows an enlarged view of a conventional magnetoresistive memory cell 10. Memory cell 10 includes a vertical stack of a diode-like selection device 11, e.g., a silicon junction diode, connected electronically in series with a magnetic tunnel junction (MTJ) device 12. Memory cell 10 can be fabricated very densely because the cell has only two terminals and has a vertical current path through selection device 11 and MTJ 12.
Selection device 11 is a silicon junction diode that is formed from an n-type silicon layer 13 and a p-type silicon layer 14. The n-type silicon layer 13 is formed on and connected to word line 3. The p-type silicon layer 14 is connected to the MTJ 12 via a tungsten stud 15. MTJ 12 is formed from a series of layers of material that are stacked one on top of the other. MTJ 12 includes a template layer 16, such as Pt, an initial ferromagnetic layer 17, such as permalloy (Ni--Fe), an antiferromagnetic layer (AF) 18, such as Mn--Fe, a fixed ferromagnetic layer (FMF) 19, such as Co--Fe or permalloy, a thin tunneling barrier layer 20 of alumina (Al2O3), a soft ferromagnetic layer (FMS) 21, such as a sandwich of thin Co--Fe with permalloy, and a contact layer 22, such as Pt. Additional details regarding conventional memory cell 10 are provided in U.S. Pat. No. 5,640,343 to Gallagher et al., which is incorporated by reference herein.
Diode 11 is necessary for preventing currents from flowing through alternate current paths, referred to herein as sneak currents. For instance, if in FIG. 1A, word line 2 is grounded and a bias of V.sub.A is applied to bit line 7, a signal current will flow through the selected cell (in this case the cell connecting word line 2 and bit line 7, referred to herein as cell 2,7). A very small current will flow through alternate paths, for example, via cells 2,6, 3,6 and 3,7 because the diode in cell 3,6 is reverse biased. The reverse currents for all of the unselected diodes in the memory matrix contribute to the total sneak current. In order to maintain the signal current to be of the same order of magnitude as the total sneak current for an n.times.n matrix, the rectification ratio of the selected diode must be greater than n.sup.2. Such a requirement for a diode requires a device-quality semiconducting diode material, which cannot easily be grown on top of a metallic word line, and implies that the diode will have a high resistance.
Additionally, the resistance of the diode, and more particularly the differential resistance of the diode, should be less than the resistance of the MTJ device so that sensing circuitry can easily detect changes in resistance of the MTJ device that represent the different states of the MTJ device. Thus, a large diode resistance implies a correspondingly large MTJ resistance so that MTJ device resistance changes can be easily detected. A high overall diode and MTJ resistance results in slow performance caused by RC delays, in addition to limited power levels during a sensing operation. A drawback associated with the Gallagher '343 memory cell is the high resistance of the diode between the two metal layers.
U.S. Pat. No. 5,734,605 to Zhu et al. discloses an alternative conventional MRAM cell that uses a transistor as a selection element for a memory cell. The Zhu et al. MRAM cell uses more space than a cross point cell because the cell has more than two terminals. Moreover, the cell must have a connection from the MTJ to the silicon surface where the transistor is located. The transistor also occupies more area than the tunnel junction occupies.
Another alternative conventional memory cell is described in U.S. Pat. No. 5,991,193 to Gallagher et al. (the Gallagher '193 patent). The memory cell disclosed in the Gallagher '193 patent uses a two-terminal, non-linear resistance semiconductor switch, such as a camel diode or backward diode containing highly doped semiconductor material. Such non-linear resistance devices can have lower resistance than a conventional diode. A cross point MRAM array formed from a vertical series connection of non-linear resistance selection device and MTJs, however, requires that the non-linear resistance devices be grown on top of a metal word lines. Growth of device-quality semiconductor material on top of a metal is exceedingly difficult and generally results in an amorphous or polycrystalline semiconductor. Accordingly, concomitant drawbacks include difficulties in achieving high active-doping densities for such non-linear resistance semiconductor switches, very high contact and series resistances, and devices having generally poor characteristics.
What is needed is a MRAM cell having only two terminals, uses a low resistance non-linear selection device, and has a vertical current path so that the selection device structure is easily fabricated on top of a metal line.